1. Field of the Invention
The present invention relates to display devices and driving methods of the devices, particularly to display devices that make a display in accordance with a scanning signal supplied from a scanning driver, and driving methods of the devices.
2. Description of the Related Art
In recent research and development of liquid crystal display devices, keen competition is held for technologies for cost reduction. In particular, a technique of forming a polysilicon thin-film transistor by a low-temperature process makes it possible to form not only a display area but also a peripheral circuit (e.g., a driver) on an inexpensive glass substrate. This technique has received a great deal of attention because the conventional cost of mounting driver ICs (Integrated Circuits) is reduced, and large cost reduction can be expected. Attempts have been made to form a polysilicon thin-film transistor on a glass substrate to manufacture a large and highly precise liquid crystal display device.
FIG. 22 shows the structure of a liquid crystal display device according to the first prior art. A display area 100 has two-dimensionally arrayed thin-film transistors. Each thin-film transistor controls display on the corresponding pixel. A first scanning driver 101a is arranged on the left side of the display area 100, while a second scanning driver 101b is arranged on the right side of the display area 100. The first and second scanning drivers 101a and 101b supply identical scanning signals to two ends of each scanning line of the display area 100 through n output lines GL1 to GLn and n output lines GR1 to GRn, respectively. First and second data drivers 102a and 102b are arranged on the upper and lower sides of the display area 100 to supply data signals to the display area 100.
A disconnection point 103 disconnects, in the display area 100, a scanning line for connecting the output line GL3 of the first scanning driver 101a and the output line GR3 of the second scanning driver 101b. In this case, since a scanning signal is supplied from the first scanning driver 101a to a display area 103a, display in the display area 103a is enabled. On the other hand, a scanning signal is supplied from the second scanning driver 101b to a display area 103b, so display in the display area 103b is enabled. That is, even when disconnection occurs at the disconnection point 103, display is enabled in both the display areas 103a and 103b. For this purpose, the two, first and second scanning drivers 101a and 101b are prepared.
Along with the recent increase in resolution of liquid crystal display devices, the numbers of output lines GL1 to GLn and GR1 to GRn of the scanning drivers 101a and 101b are increasing. As a consequence, defects during the manufacturing process readily occur in the scanning drivers 101a and 101b at high probability.
For example, the output line GR3 may be short-circuited to a power supply line or a ground line at a short-circuit point 104 in the scanning driver 101b due to a defect on the manufacturing process, as shown in FIG. 23. In this case, the output line GR3 in the scanning driver 101b is fixed to the power supply potential or ground potential, so no normal scanning signal is supplied from the scanning driver 101b to the display area 100. As a result, the right region of a horizontal line in the display area 100, which corresponds to the output line GR3, always displays white or black, and normal display is impeded.
As described above, even when the display area 100 has no defect, a defect in the scanning driver 101a or 101b makes the liquid crystal display device defective because the display area and scanning drivers are formed on a single glass substrate. A technique of correcting a defect in the scanning driver 101a or 101b has been proposed. This technique will be described next.
FIG. 24 shows the structure of a liquid crystal display device according to the second prior art disclosed in Japanese Patent Application Laid-open No. 6-67200. The liquid crystal display device of the second prior art is constructed by adding n-channel MOS (Metal Oxide Semiconductor) transistors 111a and 111b to the liquid crystal display device of the first prior art (FIGS. 22 and 23). A control signal is supplied to the gates of the transistors 111a through a control signal terminal CL. The sources and drains of the transistors 111a are connected to output lines GL1 to GLn of a first scanning driver 101a and the scanning lines in a display area 100, respectively. Similarly, a control signal is supplied to the gates of the transistors 111b through a control signal terminal CR. The sources and drains of the transistors 111b are connected to output lines GR1 to GRn of a second scanning driver 101b and the scanning lines in the display area 100, respectively.
Assume that it is detected after manufacturing the liquid crystal display device that the output line GR2 short-circuits to the power supply line or ground line at a short-circuit point 112 in the second scanning driver 101b. In this case, a high-level voltage is applied to the control signal terminal CL, and a low-level voltage is applied to the control signal terminal CR.
Consequently, the high-level voltage is applied to the gates of all of the n transistors 111a, and the n transistors 111a are turned on to connect the output lines GL1 to GLn of the scanning driver 101a to the scanning lines in the display area 100. A scanning signal is supplied from the scanning driver 101a to the display area 100.
On the other hand, the low-level voltage is applied to the gates of all of the n transistors 111b, and the n transistors 111b are turned off to disconnect the output lines GR1 to GRn of the scanning driver 101b from the scanning lines in the display area 100. No scanning signal is supplied from the scanning driver 101b to the display area 100.
That is, since a normal scanning signal is supplied only from the scanning driver 101a to the display area 100, normal display is possible. However, Japanese Patent Application Laid-open No. 6-67200 discloses no method of detecting the short-circuit point 112. Additionally, even if the defect in the second line can be visually detected on the display screen, it cannot be determined whether the defect in the second line is due to a short circuit in the scanning driver 101a or in the scanning driver 101b. Without presenting the determination method, which scanning driver has a defect, the first scanning driver 101a or second scanning driver 101b, cannot be known, and the voltage levels for the control signal terminals CL and CR cannot be determined.
Furthermore, as shown in FIG. 25, the output line GR2 may short-circuit at a short-circuit point 113 in the second scanning driver 101b, and simultaneously, a scanning line may be disconnected at a disconnection point 114 in the display area 100. In this case, assume that a high-level voltage is applied to the control signal terminal CL, and a low-level voltage is applied to the control signal terminal CR to correct the short-circuit point 113, as described above.
As a result, although a scanning signal is supplied from the first scanning driver 101a to a display area 114a, no scanning signal is supplied from either of the scanning driver 101a and 101b to a display area 114b, so normal display is disabled in the display area 114b. 
Also, as shown in FIG. 26, assume a case wherein the output line GL4 short-circuits at a short-circuit point 115 in the first scanning driver 101a, the output line GR1 short-circuits at a short-circuit point 116 in the second scanning driver 101b, and a scanning line is disconnected at a disconnection point 117 in the display area 100.
To correct the short-circuit point 116, a low-level voltage is applied to the control signal terminal CR, and a high-level voltage is applied to the control signal terminal CL. In this case, however, since the transistors 111b are turned off, and no scanning signal is supplied to a display area 117b, normal display is disabled in the display area 117b. In addition, since the output line GL4 short-circuits at the short-circuit point 115 in the first scanning driver 101a, no normal scanning signal is supplied to the fourth scanning line in the display area 100 from either of the second scanning driver 101b and the first scanning driver 101a. For this reason, the fourth line cannot be normally displayed.
On the other hand, to correct the short-circuit point 115, a low-level voltage is applied to the control signal terminal CL, and a high-level voltage is applied to the control signal terminal CR. In this case, however, since the transistors 111a are turned off, and no scanning signal is supplied to a display area 117a, normal display is disabled in the display area 117a. In addition, since the output line GR1 short-circuits at the short-circuit point 116 in the second scanning driver 101b, no normal scanning signal is supplied to the first line in the display area 100 either from the first scanning driver 101a nor from the second scanning driver 101b. For this reason, the first line cannot be normally displayed.
The above defects cannot be completely corrected. Additionally, Japanese Patent Application Laid-open No. 6-67200 presents no defect detection method, as described above. A publication that presents a defect detection method will be described next.
FIG. 27 shows the structure of a liquid crystal display device according to the third prior art disclosed in Japanese Patent No. 2973969. The liquid crystal display device of the third prior art is constructed by adding n-channel MOS transistors 121a and 121b to the liquid crystal display device of the first prior art (FIGS. 22 and 23).
Output lines GL1 to GLn of a first scanning driver 101a are connected to the gates of the n transistors 121a. An input terminal Lin and output terminal Lout are connected to the sources and drains of the n transistors 121a. 
On the other hand, output lines GR1 to GRn of a second scanning driver 101b are connected to the gates of the n transistors 121b. An input terminal Rin and output terminal Rout are connected to the sources and drains of the n transistors 121b. 
When a check signal is input to the input terminal Lin, and the signal from the output terminal Lout is checked, the state of a scanning signal supplied to the gates of the transistors 121a can be known. In addition, when a check signal is input to the input terminal Rin, and the signal from the output terminal Rout is checked, the state of a scanning signal supplied to the gates of the transistors 121b can be known. However, the third prior art discloses only the check method and no correction method.
As described above, the second prior art presents a correction method but no check method. The correction method has limitations and cannot correct the defects shown in FIGS. 25 and 26.
The third prior art discloses a check method but no correction method. Details of the check method are not presented, and all defects cannot always be detected. Even if a defect can be detected, how to correct the defect is not described.